Bipolar Junction Transistor with a Reduced Collector-Substrate Capacitance

ABSTRACT

A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance.

FIELD OF THE INVENTION

The invention relates generally to integrated circuit fabricationprocesses and structures formed according to the processes, and morespecifically to fabrication processes for forming a vertical PNPtransistor with reduced collector-substrate capacitance and vertical PNPtransistors formed according to the process.

BACKGROUND OF THE INVENTION

A plurality of integrated circuits are formed on a semiconductor waferaccording to a sequence of process steps, collectively referred to as awafer fabrication process. Each integrated circuit comprises asemiconductor substrate and semiconductor devices, such as transistors(e.g., bipolar junction transistors (BJTs) and metal-oxide semiconductorfield effect transistors (MOSFETs)) formed from doped regions within thesubstrate. Interconnect structures overlie the semiconductor substratefor electrically connecting the doped regions to form electrical devicesand circuits implementing desired electrical functions. Conventionalinterconnect structures comprise substantially horizontal dielectriclayers separating overlying and underlying substantially horizontalconductive structures comprising conductive traces or runners. Verticalconductive vias or plugs in the dielectric layers connect the horizontalconductive structures in the overlying and underlying conductive layers.The various layers and regions are formed and patterned usingconventional fabrication techniques, such as oxidation, implantation,deposition, epitaxial growth, lithography, developing, etching, andplanarization.

The sequence of process steps must be carefully designed and executed toensure that the devices are properly formed and that processesassociated with later steps do not adversely affect previously-formedstructures, as such adverse effects can impair device operation,lowering fabrication yields and increasing costs. It is also desired tolimit the number of mask steps to lower fabrication costs. Thussemiconductor manufactures desire to implement a fabrication processflow that produces properly operable transistors (e.g., PNP and NPN BJTsand MOSFETs) and other devices with a high fabrication yield.

A BJT comprises three adjacent doped semiconductor regions or layershaving an NPN or a PNP doping configuration. A middle region forms abase and two end regions form an emitter and a collector. Typically, theemitter has a higher dopant concentration than the base and thecollector, and the base has a higher dopant concentration than thecollector. Generally, the BJT can be operated as an amplifier (forexample, to amplify an input signal supplied between the base and theemitter, with the output signal appearing across the emitter/collector)or as a switch (for example, an input signal applied across thebase/emitter switches the emitter/collector circuit to an opened or aclosed state.

A MOSFET, which differs in structure and operation from a BJT, comprisessource and drain regions of a first dopant type formed in a tub or wellof a second dopant type. A voltage applied to a gate disposed above thewell between the source and drain changes a conductivity of a channelregion between the source and the drain, permitting current flow throughthe channel.

BiCMOS integrated circuits comprise both BJTs and CMOS (complementaryMOSFETs, i.e., a p-type MOSFET (PMOSFET) and an n-type MOSFET (NMOSFET))formed on the same substrate with the fabrication process steps for bothdevices integrated into one fabrication sequence. BiCMOS circuits havemany uses in the electronics industry, combining the high power and fastswitching speeds of bipolar devices with the high density and low powerconsumption of MOSFETS. The multitude of applications for BiCMOS deviceshas encouraged the development of faster and denser BiCMOS integratedcircuits with higher current capacity.

There are several known semiconductor fabrication processes for formingthe three doped layers of a BJT and several transistor architectures canbe formed according to such processes. The fabrication of NPN BJTs istypically optimized for a given process and the PNP BJTs can be “free,”i.e., certain masks are modified to form PNP BJT structures, but noadditional process steps are required. A lateral BJT structure, wherethe current flows laterally from the emitter to the collector is onetype of “free” PNP BJT.

A common vertical BJT planar structure (where the current flowsperpendicular to a plane of the substrate) comprises stacked NPN or PNPregions formed by successive dopant implants into a substrate.Significant performance enhancements are achieved by forming the emitterfrom a polysilicon layer. For example, using a polysilicon emitterallows greater control over the emitter-base doping profile. Furtherperformance enhancements are achieved by using two layers of polysilicon(referred to as a double-polysilicon BJT) one polysilicon layer for theemitter and the other for an extrinsic base. This architecture reducesbase resistance and collector-base capacitance, among other advantages.

In one embodiment the PNP BJT is fabricated on a p-type substrate,requiring the use of an n-type layer in the substrate to isolate thep-type substrate from the BJT p-type collector. A parasitic capacitanceis formed across the reverse-biased junction between the collector andthe isolating structure, referred to as a collector-substratecapacitance or a collector-n-isolation region capacitance Ccs. As isknown, this capacitance degrades high-frequency BJT performance inanalog applications and lowers BJT switching speed in digitalapplications.

A cross-sectional illustration of such a prior art vertical PNP BJT 600is illustrated in FIG. 10. The vertical PNP BJT 600 can be used, forexample, in a preamplifier application. FIG. 10 illustrates half of theregions comprising the PNP BJT 600, symmetric about a line of symmetry606.

Doped regions of the PNP BJT 600 are formed within a substrate 608 andisolated by isolation regions 610. An n-type isolation sinker region 611cooperates with an n-type isolation triple well region 612 to form atriple well isolation structure.

A collector region is indicated generally by a reference character 615,including a highly-doped collector contact surface region 614 within ap-type sinker 618. Since a subcollector region 620 is deep within thesubstrate 608 (in an embodiment having a high breakdown voltage thesubcollector region can be more than 1 micron below an upper surface ofthe substrate) the collector contact surface region 614 cannot makesatisfactory contact with the subcollector region 620, necessitating useof the p-type sinker 618. The collector 615 may also include an optionalp-type SIC (selectively implanted collector) region 622.

A polysilicon emitter 624 overlies and is separated from an n-typeintrinsic base 626 by a dielectric material layer 627. Transistor actionoccurs at the junction between the intrinsic base and the emitter. Theintrinsic base 626 contacts an n-type extrinsic base 628, aheavily-doped region that links the intrinsic base 626 to later formedconductive plugs (base contacts) in electrical communication with theextrinsic base 628.

An n-type isolation contact surface region 634 within the n-type sinkerregion 611 is biased to isolate the PNP collector regions from thep-type substrate 608.

Contact to the emitter 604 is made on a top surface of the emitterpolysilicon 604 and contact to the collector is made through thecollector contact surface region 614.

The doped regions and contacts of the PNP BJT 600 are fabricatedaccording to known fabrication processes.

The collector-n-isolation region parasitic capacitance Ccs between thesubcollector region 620 and the isolation region 612 is illustrated inphantom in FIG. 10. A peripheral or sidewall parasitic capacitance Csformed between the p-type sinker 618 and the n-type sinker region 611 isalso illustrated. As is known, both parasitic capacitances are directlyrelated to the area of the reverse biased junction and the dielectricconstant of the material, and inversely related to the width of thereverse-biased junctions across which the capacitance is formed. Bothparasitic capacitance degrade high-speed performance of the BJT.

The sidewall capacitance can be reduced by employing deep trenchisolation in which a deep trench (not shown in FIG. 10) is formedbetween the sinker regions 611 and 618. The trench is filled withsilicon dioxide. The sidewall capacitance is reduced because thedielectric constant of the silicon dioxide is about one fourth thedielectric constant of the silicon between the sinker region 618 and thesubstrate 608 when the deep trench is not present. This technique doesnot affect the collector-n-isolation region capacitance.

In yet another prior art PNP BJT the isolation triple well region isimplanted, an epitaxial layer is grown over the isolation region and thecollector is implanted in the epitaxial layer. This process controls thecollector depth to reduce the distance between the collector and theunderlying isolation region, reducing the capacitance between these twostructures. Disadvantageously, this process requires two implant stepsand the epitaxial growth step tends to introduce defects into the grownsilicon.

In another PNP BJT embodiment (not illustrated) the collector is formedproximate a buried silicon dioxide layer (e.g., a silicon-on-insulatorlayer) to reduce the collector-n-isolation region parasitic capacitance.Use of both the buried oxide layer and the deep oxide trenches providesthe lowest capacitance values for Ccs and Cs.

In yet another alternative, an n-type substrate is substituted for thep-type substrate, i.e. the PNP BJT is formed in an n-type substrate.Although this approach reduces the PNP BJT collector-isolation regionparasitic capacitance by eliminating the n-isolation region, (the reverebiased pn junction between the p-type collector and the n-type substrateprovides suitable isolation). In an application where an NPN BJT is alsofabricated on the substrate (a typical configuration), the problemsassociated with the parasitic capacitance are merely shifted from thePNP BJT to the NPN BJT. Further, a p-type substrate is generallypreferred for BiCMOS circuits in which MOSFETs and BJTs are formed.

It is therefore desired to identify process techniques and structuresthat further reduce the collector-n-isolation region capacitance Ccs.

BRIEF SUMMARY OF THE INVENTION

According to one embodiment, the present invention comprises a methodfor forming a bipolar junction transistor. The method comprisesproviding a semiconductor layer having a surface, forming spaced-apartfirst and second collector regions in the semiconductor layer, forming aburied isolation region below a lower surface of the first and thesecond collector regions and implanting a subcollector comprising firstand second end portions extending from a body portion, the first and thesecond end portions overlapping the respective first and secondcollector regions, wherein the first and the second end portions areshallower, relative to the surface, than the body portion.

According to another embodiment of the invention, a bipolar junctiontransistor comprises a semiconductor substrate having a surface, spacedapart first and second collector regions in the substrate and a thirdcollector region having a body portion and first and second end portionsextending therefrom, the first and second end portions overlapping therespective first and second collector regions, wherein the first andsecond end portions are shallower relative to the surface than the bodyportion.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more easily understood and the advantagesand uses thereof more readily apparent when the following detaileddescription of the present invention is read in conjunction with thefigures wherein:

FIGS. 1-4 are cross-sectional views of structures formed across a commonplane according to sequential processing steps of the present inventionto form a first PNP BJT.

FIGS. 5A and 5B illustrate PNP BJT doping profiles according to theprior art and according to the teachings of the present invention,respectively.

FIG. 6 illustrates dimensions for one embodiment of certain structuresof the PNP BJT of FIG. 1 as determined according to the teachings of thepresent invention.

FIG. 7 is a cross-sectional view of a second PNP BJT constructedaccording to the teachings of the present invention.

FIG. 8 is a cross-sectional view of an NPN BJT constructed according tothe teachings of the present invention.

FIG. 9 is a cross-sectional view of a BiCMOS integrated circuitcomprising a PNP BJT constructed according to the teachings of thepresent invention.

FIG. 10 is a cross-sectional view of prior art PNP BJT.

In accordance with common practice, the various described features arenot drawn to scale, but are drawn to emphasize specific featuresrelevant to the invention. Like reference characters denote likeelements throughout the figures and text.

DETAILED DESCRIPTION OF THE INVENTION

Before describing in detail exemplary methods and apparatuses related tofabrication of a vertical PNP BJT in a BiCMOS process and structuresformed according to the process to reduce the parasiticcollector-n-isolation region capacitance, it should be observed that thepresent invention resides primarily in a novel and non-obviouscombination of elements and process steps. So as not to obscure thedisclosure with details that will be readily apparent to those skilledin the art, certain conventional elements and steps have been presentedwith lesser detail, while the drawings and the specification describe ingreater detail other elements and steps pertinent to understanding theinvention. The illustrated process steps are exemplary, as one skilledin the art recognizes that certain independent steps illustrated belowmay be combined and certain, steps may be separated into individualsub-steps to accommodate individual process variations.

The teachings of the present invention are applicable to silicon PNP andNPN BJTs and to heterojunction bipolar junction transistors (HBTs),wherein the three material regions of the BJTs and the HBTs comprisesilicon, silicon-germanium, gallium-arsenide or other suitablematerials. The description below refers to an exemplary silicon PNP BJTto describe the invention.

A vertical PNP may be fabricated as follows with reference to theprocess sequence depicted in FIGS. 1-4 illustrating cross-sectionalviews of formed structures according to a sequence of exemplaryfabrication steps. The details of individual processing steps referredto herein are known in the art and need not be described in detail. Theprocess sequence is adaptable to a BiCMOS process for forming an NMOSFETand a PMOSFET (functioning as a CMOS pair) and a PNP BJT. The teachingsare also applicable to a process sequence for forming a CMOS pair, a NPNBJT and a PNP BJT on a semiconductor substrate.

Structural elements as illustrated in FIG. 1 are formed in asemiconductor substrate 12 according to known fabrication techniques,such as oxidation, implantation, deposition, diffusion, epitaxialgrowth, lithography, developing, etching, and planarization. As will beseen from the further description below, the isolation structures 16isolate an emitter, a base and a collector of the PNP BJT. Silicondioxide regions 17 span a region between adjacent isolation structures16.

P-type dopants implanted through a suitably patterned photoresiststructure form p-type sinker regions 19. N-type dopants implantedthrough a suitably patterned photoresist structure form n-type sinkerisolation regions 32. An n-type triple well isolation region 36 isformed by implanting n-type dopants through an appropriately patternedphotoresist structure. Exemplary implant conditions for forming thetriple well isolation region 36 comprise phosphorous implanted at 1200keV with a density of 4E12 per cm³. Spaced-apart lateral ends 36A of then-type triple well isolation region 36 overlap with lower ends of then-type sinker isolation regions 32 to form an n-type triple wellisolation tub surrounding the p-type sinker regions 19 and otherlater-formed PNP BJT structures.

Structures 45 overlying isolation structures 16A and 16B are formed bydepositing and patterning one or more material layers. In an embodimentwhere MOSFETS are formed in the substrate 12, the structures 45 can eachcomprise a MOSFET gate stack. Other suitable materials (includingdielectric materials) may be used to form the structures 45. The gatestacks are formed by blanket depositing a gate oxide layer, polysiliconlayer (doped in situ or by implant doping) and a tungsten layer. Thepolysilicon and tungsten layers ate etched according to a pattern in anoverlying patterned photoresist layer or, more commonly in an overlyinghard mask layer. In the latter case, each gate stack comprises apolysilicon layer, a tungsten silicide layer (formed from thepolysilicon and tungsten) and a hard mask layer. In one embodiment thegate stacks, and thus the structures 45, are about 300 nm thick.

Through a patterned photoresist structure 70 (see FIG. 2), a high-energyp-type implant forms a PNP BJT subcollector 72 (overlapping the p-typesinker regions 19) and a collector 73. One exemplary subcollectorimplant condition uses boron at about 1200 keV and a dose of about 6E13per cm³.

The structures 45 overlying the isolation structures 16A and 16B reducethe implant range of the implanted subcollector 72 over portions of thesubcollector 72 underlying the structures 45, forming end regions 72Aoverlapping the p-type sinker regions 19 and spaced vertically apartfrom the n-type triple well isolation region 36. The implant range isreduced by a distance about equal to a thickness of the structures 45.

This spaced-apart end regions 72A in the subcollector 72 reduce thecollector-n-isolation region capacitance since the capacitance isinversely proportional to the distance between the charged regions ofthe reverse biased junction formed between the p-type collector and then-type isolation region. This feature also reduces the collectorresistance because the subcollector end regions 72A are each closer to arespective collector contact surface region formed later in a surface ofthe sinker regions 19.

Continuing with FIG. 2, a low energy n-type implant forms a PNP BJT base74.

The teachings of the present invention can be applied to the formationof a PNP BJT in various types of integrated circuits, including a BiCMOSintegrated circuit including both BJTs and MOSFETs. In this application,a spacer oxide layer is formed over a substrate surface to form spacersadjacent the MOSFETs gate stacks. Such a spacer oxide layer 82 isillustrated in FIG. 3. A PNP emitter window is formed in the spaceroxide layer 82 and an underlying screen oxide layer 54 by etchingthrough an opening in a patterned photoresist structure. An optional SICimplant can be made through the window to form a selectively implantedcollector region (not shown). After cleaning the substrate, apolysilicon layer 150 is deposited over the upper surface of thesubstrate 12 and within the emitter window as illustrated in FIG. 3.Boron or another p-type dopant is implanted into the polysilicon layer150 or the layer is doped in situ.

According to an appropriately patterned mask, the polysilicon layer 150is etched to form a PNP emitter 150A. See FIG. 4. The spacer oxide layer82 is etched to form gate stack spacers for the MOSFETS (notillustrated) and spacer regions 212 laterally adjacent the structures45.

N+ extrinsic base regions 236 are formed in spaced-apart end regions ofthe base 74 by implant doping through a patterned mask. N+ high-dopantdensity contact surface regions 238 are formed in the sinker isolationregions 32.

Using a patterned implant mask, high-dopant density collector surfaceregions 264 are formed in a surface of the PNP collector regions 19 asillustrated in FIG. 4.

An edge 270 of each one of the structures 45 is preferably located toavoid overlap with the extrinsic base regions 236 (as any overlap candetrimentally affect the implant doping that forms the extrinsic baseregions 236) and also to maintain a suitable base-collector breakdownvoltage, i.e., avoid reducing a distance between the subcollector 72 andthe base 74 that lowers the base-collector breakdown voltage. A width ofthe structures 45 must also consider a width of the underlying isolationstructures 16A and 16B.

An edge 280 of each one of the structures 45 is preferably locatedwithin an opening of a subcollector mask through which the subcollector72 is formed, ensuring that a distance between the subcollector 72 andthe n-isolation region 36 is greater at the end portions 72A than atother regions of the subcollector 72.

A silicon dioxide layer (not shown) is formed (typically according to ahigh-density plasma deposition process) to encapsulate the substrate 12and the structures formed therein to prevent the dopant atoms fromevaporating from the semiconductor material during a subsequent annealprocess. The substrate 12 is annealed to repair crystal lattice damageresulting from collisions between the implanted n-type and p-typedopants and the lattice atoms and to electrically activate the implanteddopants.

Conventional processing steps (referred to as backend process steps) areperformed to passivate the upper surface of the substrate 12, fabricateinterconnect structures and package the device. A first dielectric layerand a first conductive layer are deposited overlying the substrate 12 toform a first layer interconnect (not shown in the Figures). The firstlevel interconnect structures comprise conductive plugs formed in thedielectric layer for contacting the PNP emitter 150B, the PNP extrinsicbases 236, the high-dopant density contact surface regions 238 in thesinker isolation regions 32 and the PNP high-dopant density collectorcontact surface regions 264.

FIGS. 5A and 5B illustrate region doping profiles for a PNP BJT of theprior art (FIG. 5A) and for a PNP BJT fabricated according to thepresent invention (FIG. 5B). As can be seen, the subcollector dopingprofile is shifted toward the surface of the semiconductor layer by theabout 0.3 um, which is the approximate thickness of the structures 45.The doping profile of the n-type isolation region (i.e., the triple well36) remains unchanged between the two Figures since it is formed priorto formation of the inventive structures 45. The increased separation ofthe highly doped regions of the subcollector and the n-type isolationregion reduces the collector-n-isolation region junction capacitance.

FIG. 6 illustrates approximate dimensions for certain structures formedaccording to one embodiment of the present invention. The implant rangefor the dopants implanted to form the subcollector 72 is affected (aboutone-for-one) by the height of the structures 45 above an upper surface12A of the substrate 12. As can be seen, the structure 45 is about 0.3μm thick, raising the deposition depth of the end regions 72A about 0.4μm above the subcollector 72. The additional 0.1 μm is contributed by anupper region of the isolation structure 16 that is about 0.1 μm abovethe upper surface 12A. This figure comports with the doping profilesillustrated in FIG. 5B as described above.

Use of the structures 45 also ensures that the base implant (i.e., thebase 74 implanted as described in conjunction with FIG. 2) does notextend to a region below the isolation structures 16A and 16B.Preferably, the base should be implanted in the surface of the substrate12 between the isolation structures 16A and 16B, i.e., to contact theemitter region 150B and the extrinsic base regions 236 (see FIG. 4). Ifthe base implants extend below the isolation structures 16A and 16B,i.e., in a direction toward the collector contacts 264 of FIG. 4, abase-collector capacitance increases responsive to the decreaseddistance between the base and the collector regions 19. The structures45 overlying the isolation structures 16A and 16B cause the implantingdopants to lose energy as they travel through these structures. Thereduced dopant energy shifts the implanted base upwardly, ensuring thatthe base implant does not dope regions below the isolation structures16A and 16V and increase the base-collector capacitance. The spacers 212further expand the design space for the base 74, allowing the baseimplant with heavier implanting ions, since the spacers 212 will alsoprevent those ions from reaching the substrate 12 below the isolationstructures 16A and 16B.

In an embodiment where the structures 45 comprise MOSFET gate stacks,the polysilicon material layer in the gate stack can be connected toground, forming a shield or field plate to limit cross talk orelectrical interference between devices.

The process according to the present invention for decreasing thecapacitance between the PNP collector and the n-isolation region iseasily adaptable to current fabrication process flows as no additionalprocessing steps are required. Only different mask configurations arerequired. For example, although described with reference to a PNP BJTemitter formed from a polysilicon layer and an implanted base, theteachings of the present invention can also be applied to a PNP BJTcomprising an extrinsic base and an emitter each formed from separatepolysilicon layers, and can be applied to a PNP BJT comprising animplanted emitter and an implanted base.

While the process of the invention has been described with reference toa PNP BJT having a single polysilicon emitter region (150B) intermediateextrinsic base regions (236), the teachings of the present invention canalso be applied to a BJT having two spaced-apart emitter regions with abase region intermediate thereto as further described and claimed incommonly owned patent application entitled Processes for Forming BipolarJunction Transistors and Bipolar Junction Transistors Formed Accordingto the Processes, (attorney docket number Chen 21-1-15-7-9/075903-464)filed on ______ and assigned application number ______, the teachings ofwhich are herein incorporated by reference. FIG. 7 illustrates a PNP BJTcomprising emitter regions 300A and 300B with an extrinsic base region302 intermediate the emitter regions.

The process of the present invention can also be applied to thefabrication of an NPN BJT in an n-type substrate for reducingcapacitance between the NPN BJT collector and the underlying p-typeisolation region and the fabrication of an NPN BJT in an n-type wellformed in a p-type substrate. An NPN BJT 360 of FIG. 8 formed in ann-type well 362, which is formed in a p-type substrate 364, comprisesp-type isolation sinker regions 368 cooperating with a p-type triplewell isolation region 372 to form a triple well isolation tubsurrounding the structures of the NPN BJT 360. Collector sinker regions380 overlap end portions 384A of a subcollector 384. The end portions384A are shallower than other regions of the subcollector 384 due to theimplant range-reduction effects of structures 388 overlying isolationregions 16A and 16B. The NPN BJT further comprises a base 390 and anemitter 392. A high-dopant density contact surface region 396 isdisposed in each collector sinker region 380 and a high-dopant densitycontact surface region 400 is disposed in each isolation sinker region368 for connecting these regions, through conductive vias in contactwith the high-dopant density contact surface regions, to other devicesformed in the substrate 364.

The process for forming the PNP transistor of the present invention canalso be applied to a complementary BiCMOS process and structures formedaccording to the process. Generally, it will be appreciated that one canfabricate the novel device independently of its application to anyspecific process or in conjunction with the fabrication of other devicesin the substrate. FIG. 9 illustrates an NMOSFET 420 formed in a p-tub422, a PMOSFET 426 formed in an n-tub 430, a NPN BJT 434 and a PNP BJT438, the latter constructed according to the teachings of the presentinvention as described in conjunction with FIGS. 1-4. The NMOSFET 420further comprises lightly-doped regions 450, source/drain regions 454, agate stack 458 and sidewall spacers 462. The PMOSFET 426 furthercomprises lightly-doped regions 470, source/drain regions 474, the gatestack 458 and the sidewall spacers 462. The NPN BJT comprises acollector sinker region 480 and an overlapping subcollector 481, both inan n-tub 482, an extrinsic base polysilicon structure 483, an intrinsicbase 484, an emitter polysilicon structure 486, intermediate dielectricmaterial layers 488 and 490 and a high dopant-density collector contactsurface region 492. In this embodiment, the structures 45 compriseMOSFET gate stacks formed simultaneously with the NMOSFET and PMOSFETgate stacks 458.

It should also be recognized that while the embodiment describedutilizes compounds or elements commonly employed in today's technologyas dopants, isolation layers and the like, it is possible to substituteother materials that function in the same manner for the preferredmaterials of today's technology.

Although the present invention has been described with reference topreferred embodiments, it will be understood by those skilled in the artthat various changes may be made and equivalent elements may besubstituted for the elements thereof without departing from the scope ofthe invention. The scope of the present invention further includes anycombination of elements from the various embodiments set forth herein.In addition, modifications may be made to adapt a particular situationto the teachings of the present invention without departing from itsessential scope. Therefore, it is intended that the invention not belimited to the particular embodiments disclosed, but that the inventionwill include all embodiments failing within the scope of the appendedclaims.

1. A method for forming a bipolar junction transistor, comprising:providing a semiconductor layer having a surface; forming spaced-apartfirst and second collector regions in the semiconductor layer; forming aburied isolation region below a lower surface of the first and thesecond collector regions; implanting a subcollector comprising first andsecond end portions extending from a body portion, the first and thesecond end portions overlapping the respective first and secondcollector regions, wherein the first and the second end portions areshallower, relative to the surface, than the body portion.
 2. The methodof claim 1 further comprising forming a first and a second structureprior to the implanting step for slowing implanting ions that form thefirst and the second end portions.
 3. The method of claim 2 wherein thestep of forming the first and the second structures comprises formingthe first and the second structures overlying a region of thesemiconductor layer where the first and the second end portions are tobe formed.
 4. The method of claim 2 wherein a region of maximum dopantdensity of the subcollector is shifted toward the surface by a distanceabout equal to a height of the first and the second structures above thesurface.
 5. The method of claim 1 further comprising formingspaced-apart first and second isolation structures in an upper region ofthe semiconductor layer, forming third and fourth structures overlyingthe respective first and second isolation structures, wherein the thirdand the fourth structures slow implanting ions that form the first andthe second end portions.
 6. The method of claim 1 further comprising:forming a third collector region overlying the subcollector; forming abase in contact with the third collector region; forming an emitter incontact with the base; and forming spaced-apart first and secondisolation sinkers each overlapping an end region of the buried isolationregion, the first and the second isolation sinkers and the buriedisolation region cooperating to form an isolation tub for the bipolarjunction transistor.
 7. The method of claim 1 wherein a capacitancebetween the subcollector and a region of the semiconductor layerthereunder decreases as a distance between an upper surface of theburied isolation region and a lower surface of the first and the secondend portions increases.
 8. The method of claim 1 wherein the bipolarjunction transistor comprises a PNP bipolar junction transistor and thesemiconductor layer comprises a p-type semiconductor layer or thebipolar junction transistor comprises an NPN bipolar junction transistorand the semiconductor layer comprises an n-type semiconductor layer. 9.The method of claim 1 further comprising forming a first and a secondstructure prior to the step of implanting the subcollector to form thefirst and the second end portions, wherein the step of forming the basefurther comprises implanting the base, and wherein during the step ofimplanting the base the first and the second structures limit a lateralextent of the base by slowing implanting ions forming the base.
 10. Amethod for forming a bipolar junction transistor and a metal oxidesemiconductor field effect transistor in a semiconductor layer,comprising: providing the semiconductor layer having a surface; formingMOSFET structures in a MOSFET region of the semiconductor layer; forminga first gate stack in the MOSFET region and second and third gate stacksin a bipolar junction transistor region; forming spaced-apart first andsecond collector regions in the bipolar junction transistor region;forming a buried isolation region below a lower surface of each of thefirst and the second collector regions and extending between the firstand the second collector regions; and implanting a subcollector throughthe second and the third gate stacks and a region of the semiconductorlayer therebetween, wherein the subcollector comprises a body portionand first and second end portions extending therefrom, the first andsecond end portions overlapping the respective first and secondcollector regions, and wherein the first and second end portions areshallower, relative to the surface, than the body portion.
 11. Themethod of claim 10 further comprising forming spaced-apart first andsecond isolation structures in an upper region of the semiconductorlayer, wherein the step of forming the first, second and third gatestacks further comprises forming the second and the third gate stacksoverlying the respective first and second isolation structures, andwherein the second and third gate stacks slow implanting ions that formthe first and the second end portions.
 12. The method of claim 10further comprising: forming a third collector region overlying thesubcollector; forming a base in contact with the third collector region;forming an emitter in contact with the base; and forming spaced-apartfirst and second isolation sinkers each overlapping an end region of theburied isolation region, the first and the second isolation sinkers andthe buried isolation region cooperating to form an isolation tub for thebipolar junction transistor.
 13. The method of claim 10 whereincapacitance between the subcollector and a region of the semiconductorlayer and the buried isolation region decreases as the distance betweenthe upper surface of the buried isolation region and the lower surfaceof the first and the second end portions increases.
 14. A bipolarjunction transistor comprising: a semiconductor substrate having asurface; spaced apart first and second collector regions in thesubstrate; and a third collector region having a body portion and firstand second end portions extending therefrom, the first and second endportions overlapping the respective first and second collector regions,wherein the first and second end portions are shallower relative to thesurface than the body portion.
 15. The bipolar junction transistor ofclaim 14 further comprising first and second structures overlying tiesurface and substantially vertically aligned with the first and thesecond end portions of the third collector region.
 16. The bipolarjunction transistor of claim 14 further comprising first and secondisolation structures overlapping end regions of a third isolationstructure formed in the substrate, wherein the first, second and thirdisolation structures comprises an isolation tub for the bipolar junctiontransistor.
 17. The bipolar junction transistor of claim 14 comprising aPNP bipolar junction transistor formed in a p-type substrate or an NPNbipolar junction transistor formed in an n-type substrate.
 18. Thebipolar junction transistor of claim 14 further comprising a base inconductive communication with the third collector region and an emitterin contact with the base.
 19. A BiCMOS circuit comprising: asemiconductor substrate having a surface; in a MOSFET region of thesubstrate: a doped tub; a source and a drain in the doped tub; a firstgate stack overlying the doped tub intermediate the source and thedrain; in a BJT region of the substrate: spaced apart first and secondisolation structures in the surface; second and third gate stacksoverlying the respective first and second isolation structures; spacedapart first and second collector structures; a subcollector having abody portion and first and second end portions extending therefrom, thefirst and second end portions overlapping the respective first andsecond collector structures; a third collector structure overlying thesubcollector; a base in contact with the third collector structure; anemitter in contact with the base; and an isolation structure boundingthe first, second and third collector structures and the subcollector,the isolation structure comprising a buried isolation structure below alower surface of the first and the second collector structures and belowa lower surface of the subcollector, and wherein the end portions areshallower relative to the surface than the body portion.
 20. The BiCMOScircuit of claim 19 comprising a PNP bipolar junction transistor formedin a p-type substrate or an NPN bipolar junction transistor formed in ann-type tub formed in a p-type substrate.